Discrete wavelet transform

Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures

Distributed Computing / Computer Hardware / Processor Architecture / Reconfigurable Hardware / Software Implementation / Field Programmable Gate Array / Data transfer / Load distribution / Partial Reconfiguration / Discrete wavelet transform / Divisible Load Theory / Electrical And Electronic Engineering / RECONFIGURABLE LOGIC / Finite Impulse Response (FIR) / Field Programmable Gate Array / Data transfer / Load distribution / Partial Reconfiguration / Discrete wavelet transform / Divisible Load Theory / Electrical And Electronic Engineering / RECONFIGURABLE LOGIC / Finite Impulse Response (FIR)